Slow-speed transmission of multi-bit words typically occurs over multi-wire buses. For example, an eight-bit word may be transmitted over a bus having eight wires, one for each bit. But in such conventional busses, each bit propagates independently of the remaining bits. As the data rates increase, such parallel data transmission becomes problematic in that the various bits in a word become skewed from each other as the word propagates over the bus.
Given the issues with skew between multiple bits in high-speed communication, various serializer/deserializer (SerDes) systems have been developed. A SerDes transmitter serializes a multi-bit word into a serial stream of corresponding bits for transmission to a receiver. There can then be no such skew between adjacent bits as occurs in parallel transmission since a single transmission line (which may be differential) is used for the serial data stream. The SerDes receiver deserializes the received serial bit stream into the original word. However, the transmission line and the receiver load introduce distortion into the serial data stream as the data transmission rate exceeds, for example, 10 GHz. Adjacent bits in the serial data stream then begin to interfere with each other. Complicated equalizing schemes become necessary to fight the resulting inter-symbol interference and thus it becomes difficult to push SerDes data transmission rates even higher.
To increase data transmission rates over the SerDes limitations, a three-level signaling protocol has been developed in which three transmitters drive three separate transmission lines. The three transmitters may be either voltage-mode or current-mode transmitters. Since the net current must be zero, all three transmitters cannot be active (either transmitting or receiving current) in a three-level signaling system. Similarly, there must be current injected and received so all three transmitters cannot be inactive for any given symbol. So that means that two of the three transmitters will be active for each symbol, with one sourcing current and the other receiving current. From a set of three transmitters, there are three distinct pairs of transmitters that can be active. Within each pair, there are two possibilities depending upon which transmitter is sourcing versus which transmitter is receiving. There are thus six distinct combinations of two active transmitters each sourcing or receiving a given amount of current in a three-transmitter multi-level system. Each distinct combination of active transmitters may be denoted as a symbol. Since there are six possible symbols, each transmitted symbol represents 2.5 bits. In this fashion, data transmission speeds may be more than doubled over binary transmission at the same symbol rate using a single channel, albeit at the cost of increased power consumption.
The three transmitted signals may be designated as signals A, B, and C, respectively. The binary values of these signals depend upon a number of factors such as the power supply voltage and the termination resistances. In the following examples, the binary high voltage is assumed to be 300 mV whereas the binary low voltage is assumed to be 100 mV. The remaining signal voltage will be approximately one-half of the binary high voltage (in this example, 200 mV). However, it will be appreciated that these voltage values are merely exemplary and may be varied in alternative implementations. It is conventional to receive the three transmitted signals using three high-speed receiver equalizers. However, the amplitudes of the received signals may be too low for equalization to proceed efficiently due to propagation losses. It is thus also conventional to boost the amplitude of the received signals prior to equalization. The three received signals prior to amplification may be designated as signals A, B, and C. Received signal A would thus be amplified to form into an amplified (which may also be designated as level-shifted) signal AO. Similarly, received signal B would be amplified to form an amplified signal BO, and received signal C would be amplified to form an amplified signal CO.
It is conventional to perform the amplification using three high-speed receiver amplifiers as shown in FIG. 1A. A first receiver amplifier 100 includes a differential pair of PMOS transistors P1 and P2. The received signal A drives the gate of transistor P1 whereas received signal B drives the gate of transistor P2. The drains of transistors P1 and P2 couple to ground through respective resistors R. The drain of transistor P1 drives an output signal AO. Similarly, the drain of transistor P2 drives an output signal BO. A current source of I drives the sources of transistors P1 and P2.
A second receiver amplifier 105 is analogous to receiver 100 in that it includes a differential pair of PMOS transistors P3 and P4. Received signal B drives the gate of transistor P3 whereas a received signal C drives the gate of transistor P4. Resistors R and a current source providing a current I are arranged as discussed with regard to receiver amplifier 100. The drain of transistor P3 drives output signal BO. Similarly, the drain of transistor P4 drives an output signal CO.
A third receiver 110 is also analogous to receiver 100 in that it includes a differential pair of PMOS transistors P5 and P6. Received signal C drives the gate of transistor P5 whereas received signal A drives the gate of transistor P6. Resistors R and a current source providing a current I are arranged as discussed with regard to receiver amplifier 100. The drain of transistor P5 drives output signal CO. Similarly, the drain of transistor P6 drives output signal AO.
The three resulting receiver amplifiers 100, 105, and 110 thus consume 3*I total current. Such current consumption is exacerbated as additional channels are used (each channel corresponding to its own trio of signals A, B, and C). Moreover, inevitable mismatches between the differential pair transistors exacerbate the bit error rate. In addition, the use of three differential receiver amplifiers for each trio of signals demands significant die space. Accordingly, there is a need in the art for receiver amplifiers with increased density, reduced power consumption, and reduced layout mismatch for multi-level signaling systems.
The amplified signals AO, BO, and CO may then be equalized in receiver equalizers such as shown in FIG. 1B. A first receiver equalizer 115 includes a differential pair of PMOS transistors P7 and P9. Amplified signal AO drives the gate of transistor P7 whereas amplified signal BO drives the gate of transistor P8. The drains of transistors P7 and P8 couple to ground through respective resistors R0. The drain of transistor P7 drives an output signal AO′. Similarly, the drain of transistor P8 drives an output signal BO′. A current source of a current I drives the source of transistor P7. Similarly, another current source of current I drives the source of transistor P8. To accentuate the high-frequency gain, the common source for transistors P7 and P8 is degenerated by a capacitor Cs that couples in parallel with a resistor Rs between the sources of transistors P7 and P8.
A second receiver equalizer 120 is analogous to receiver equalizer 115 in that it includes a differential pair of PMOS transistors P9 and P10. Amplified signal BO drives the gate of transistor P9 whereas amplified signal CO drives the gate of transistor P10. Resistors R0, capacitor Cs, resistor Rs, and the pair of current sources each providing a current I are arranged as discussed with regard to receiver equalizer 115. The drain of transistor P9 drives output signal BO′. Similarly, the drain of transistor P10 drives an output signal CO′.
A third receiver equalizer 125 is also analogous to receiver equalizer 115 in that it includes a differential pair of PMOS transistors P11 and P12. Amplified signal CO drives the gate of transistor P11 whereas amplified signal AO drives the gate of transistor P12. Resistors R0, capacitor Cs, resistor Rs, and the pair of current sources each providing a current I are arranged as discussed with regard to receiver equalizer 115. The drain of transistor P11 drives output signal CO′. Similarly, the drain of transistor P12 drives output signal AO′.
The three resulting receiver equalizers 115, 120, and 125 thus consume 6*I total current. Such current consumption is exacerbated as additional channels are used (each channel corresponding to its own trio of signals A, B, and C). Moreover, inevitable mismatches between the differential pair transistors exacerbate the bit error rate. In addition, the use of three receiver equalizers for each trio of signals demands significant die space. Accordingly, there is a need in the art for equalizers with increased density, reduced power consumption, and reduced layout mismatch for multi-level signaling systems.